Electrostatic charge is defined as “electric charge at rest”. Static electricity is an imbalance of electrical charges within or on the surface of a material. This imbalance of electrons produces an electric field that can be measured and that can influence other objects. Electrostatic discharge (ESD) is defined as the rapid, spontaneous transfer of electrostatic charge induced by a high electrostatic field. Electrostatic discharge can change the electrical characteristics of a semiconductor device, degrading or destroying it. With both the need for increased performance (devices that operate at 1 GHz and higher and high speed serial link input/outputs that operate at 20-30 gigabit per second) and the increase in the density of circuits (Moore's Law) on a device, integrated circuits are expected to become more sensitive to ESD events. This trend may be accelerating.
An ESD event will force a current pulse from few hundred milliamps to several tens of amps into the integrated circuit for a time period ranging from few nanoseconds to several microseconds. Typical power levels that need to be dissipated during an ESD event are on the order of several tens of watts. An ESD protection circuit can be used to shunt the ESD current through the unpowered IC along the intended ESD protection path, while clamping the voltage at a safe level, without causing any IC functional performance degradation. An ESD protection mechanism should therefore have the ability to protect the circuit and the components to which it is connected. This may include a fast turn-on of ESD protection device, which minimizes the voltage clamping level, and shunts ESD energy away from the protected circuit area.
To ensure a robust ESD protection design, ESD protection evaluation and verification needs to be done at every stage of an overall integrated circuit design flow. Today's electronic design automation tool landscape offers a wide range of options for rule-based ESD verification. Designers may identify the protection schemes, write a pattern template for each protection scheme as an input for a verification tool and run the verification tool to automatically identify whether these patterns are present on all input/output pads in a design.
As technology scaling continues, meeting product ESD targets becomes more challenging. At 14 nm and below, for example, the physical area taken by ESD protection devices often appear to be getting bigger compared to the rapidly shrinking logic devices. This puts pressure on making sure the protection devices are sized just right to meet ESD performance without excessive margin. Another example is that the interconnect stack tends to favor more thin metal layers, which can increase the interconnect resistance to a level unseen in earlier technology nodes. Under such conditions, a rule-based ESD verification approach is not sufficient. A full-circuit (full-chip) simulation-based approach can provide a more accurate and comprehensive analysis.
A full-circuit current density simulation faces many challenges given the large sizes of modern IC designs. Parasitic extraction can generate a vast amount of data for the power, ground and pad nodes. The peak memory usage during simulation can make the full-circuit simulation-based analysis impractical. A reduction of parasitic resistance data needed for simulation without severely affecting accuracy is desirable.